uMIPS is a 32-bit pipelined processor implementing the MIPS1 ISA, written in synthesizable Verilog and tested on a DE0 CycloneIII FPGA board. A great deal of the ISA is implemented, enough to run small C programs compiled with the gcc toolchain.
The design is based on a classic five-stage pipeline, fetch, decode, execute, memory and write-back stages, each one is represented by an architectural state register, it's worth...
