MIPS1 ISA Implementation with Verilog

uMIPS is a 32­-bit pipelined processor implementing the MIPS1 ISA, written in synthesizable Verilog and tested on a DE0 CycloneIII FPGA board. A great deal of the ISA is implemented, enough to run small C programs compiled with the gcc toolchain.

The design is based on a classic five-stage pipeline, fetch, decode, execute, memory and write-back stages, each one is represented by an architectural state register, it's worth mentioning that it's enough to save and restore those registers for a context switch if needed. Separate data and instruction memories are used, each one is initialized with a memory hex file generated by the toolchain.

The design includes a hazard unit that solves control and data hazards by forwarding or stalling the pipeline whenever is necessary and some registers are memory mapped to high addresses to control the LED strip on the board and the 2x16 LCD screen.

Testing
I tested the processor successfully by running a program that computes the factorial of a number and the LCD driver.

Todo

• Dynamic branch prediction.
• Load programs from Flash and link to libc.
• Exceptions/Interrupts coprocessor.
• The instruction memory does not get inferred properly.

Sources

hg clone https://code.google.com/p/umips/ 

References
David Harris, Sarah Harris. "Digital Design and Computer Architecture"
David A. Patterson, John L. Hennessy. “Computer Organization and Design”, 4th Edition.